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document no. e0148h20 (ver. 2.0) date published april 2002 (k) japan url: http://www.elpida.com ? elpida memory, inc. 2001-2002 ? hitachi, ltd. 2001 elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. preliminary data sheet 256mb ddr sdram s.o.dimm hb54a2568kn-a75b/b75b/10b (32m words 64 bits, 2 banks) description the hb54a2568kn is double data rate (ddr) sdram module, mounted 256m bits ddr sdram (hm5425161btt) sealed in tsop package, and 1 piece of serial eeprom (2k bits eeprom) for presence detect (pd). the hb54a2568kn is organized as 16m 64 2 bank mounted 8 pieces of 256m bits ddr sdram. read and write operations are performed at the cross points of the ck and the /ck. this high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. data strobe (dqs) both for read and write are available for high speed and reliable data bus design. by setting extended mode register, the on-chip delay locked loop (dll) can be set enable or disable. an outline of the products is 200-pin socket type package (dual lead out). therefore, it makes high density mounting possible without surface mount technology. it provides common data inputs and outputs. decoupling capacitors are mounted beside each tsop on the module board. features ? 200-pin socket type package (dual lead out) ? outline: 67.6mm (length) 31.75mm (height) 3.80mm (thickness) ? lead pitch: 0.6mm ? 2.5v power supply (vcc) ? sstl-2 interface for all inputs and outputs ? clock frequency: 133 mhz (max) (-a75b/b75b) : 100 mhz (max) (-10b) ? data inputs, outputs and dm are synchronized with dqs ? 4 banks can operate simultaneously and independently (component) ? burst read/write operation ? programmable burst length: 2, 4, 8 ? burst read stop capability ? programmable burst sequence ? sequential ? interleave ? start addressing capability ? even and odd ? programmable /cas latency (cl): 2, 2.5 ? 8192 refresh cycles: 7.8 s (8192row /64ms) ? 2 variations of refresh ? auto refresh ? self refresh
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 2 ordering information part number clock frequency mhz (max.) /cas latency package contact pad hb54a2568kn-a75b* 1 hb54a2568kn-b75b* 2 hb54a2568kn-10b* 3 133 mhz 133 mhz 100 mhz 2.0 2.5 2.0 200-pin dual lead out socket type gold notes: 1. 143 mhz operation at /cas latency = 2.5. 2. 100 mhz operation at /cas latency = 2.0. 3. 125 mhz operation at /cas latency = 2.5. pin configurations 1 pin 2 pin front side back side 39 pin 40 pin 41 pin 42 pin 199 pin 200 pin pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vref 51 vss 2 vref 52 vss 3 vss 53 dq19 4 vss 54 dq23 5 dq0 55 dq24 6 dq4 56 dq28 7 dq1 57 vcc 8 dq5 58 vcc 9 vcc 59 dq25 10 vcc 60 dq29 11 dqs0 61 dqs3 12 dm0 62 dm3 13 dq2 63 vss 14 dq6 64 vss 15 vss 65 dq26 16 vss 66 dq30 17 dq3 67 dq27 18 dq7 68 dq31 19 dq8 69 vcc 20 dq12 70 vcc 21 vcc 71 nc 22 vcc 72 nc 23 dq9 73 nc 24 dq13 74 nc 25 dqs1 75 vss 26 dm1 76 vss 27 vss 77 nc 28 vss 78 nc 29 dq10 79 nc 30 dq14 80 nc 31 dq11 81 vcc 32 dq15 82 vcc 33 vcc 83 nc 34 vcc 84 nc 35 ck0 85 nc 36 vcc 86 nc 37 /ck0 87 vss 38 vss 88 vss 39 vss 89 ck2 40 vss 90 vss 41 dq16 91 /ck2 42 dq20 92 vcc 43 dq17 93 vcc 44 dq21 94 vcc 45 vcc 95 cke1 46 vcc 96 cke0 47 dqs2 97 nc 48 dm2 98 nc 49 dq18 99 a12 50 dq22 100 a11
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 3 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 101 a9 151 dq42 102 a8 152 dq46 103 vss 153 dq43 104 vss 154 dq47 105 a7 155 vcc 106 a6 156 vcc 107 a5 157 vcc 108 a4 158 /ck1 109 a3 159 vss 110 a2 160 ck1 111 a1 161 vss 112 a0 162 vss 113 vcc 163 dq48 114 vcc 164 dq52 115 a10/ap 165 dq49 116 ba1 166 dq53 117 ba0 167 vcc 118 /ras 168 vcc 119 /we 169 dqs6 120 /cas 170 dm6 121 /s0 171 dq50 122 /s1 172 dq54 123 nc 173 vss 124 nc 174 vss 125 vss 175 dq51 126 vss 176 dq55 127 dq32 177 dq56 128 dq36 178 dq60 129 dq33 179 vcc 130 dq37 180 vcc 131 vcc 181 dq57 132 vcc 182 dq61 133 dqs4 183 dqs7 134 dm4 184 dm7 135 dq34 185 vss 136 dq38 186 vss 137 vss 187 dq58 138 vss 188 dq62 139 dq35 189 dq59 140 dq39 190 dq63 141 dq40 191 vcc 142 dq44 192 vcc 143 vcc 193 sda 144 vcc 194 sa0 145 dq41 195 scl 146 dq45 196 sa1 147 dqs5 197 vccspd 148 dm5 198 sa2 149 vss 199 vccid 150 vss 200 nc
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 4 pin description pin name function a0 to a12 address input row address a0 to a12 column address a0 to a8 ba0, ba1 bank select address dq0 to dq63 data input/output /ras row address strobe command /cas column address strobe command /we write enable /s0, /s1 chip select cke0, cke1 clock enable ck0 to ck2 clock input /ck0 to /ck2 differential clock input dqs0 to dqs7 input and output data strobe dm0 to dm7 input mask scl clock input for serial pd sda data input/output for serial pd sa0 to sa2 serial address input vcc power for internal circuit vccspd power for serial eeprom vref input reference voltage vss ground vccid vcc identification flag nc no connection
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 5 serial pd matrix* 1 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes utilized by module manufacturer 1 0 0 0 0 0 0 0 80 128 1 total number of bytes in serial pd device 0 0 0 0 1 0 0 0 08 256 byte 2 memory type 0 0 0 0 0 1 1 1 07 sdram ddr 3 number of row address 0 0 0 0 1 1 0 1 0d 13 4 number of column address 0 0 0 0 1 0 0 1 09 9 5 number of dimm banks 0 0 0 0 0 0 1 0 02 2 6 module data width 0 1 0 0 0 0 0 0 40 64 bits 7 module data width continuation 0 0 0 0 0 0 0 0 00 0 (+) 8 voltage interface level of this assembly 0 0 0 0 0 1 0 0 04 sstl 2.5v 9 ddr sdram cycle time, cl = x -a75b 0 1 1 1 0 0 0 0 70 cl = 2.5* 5 -b75b 0 1 1 1 0 1 0 1 75 -10b 1 0 0 0 0 0 0 0 80 10 sdram access from clock (tac) -a75b/b75b 0 1 1 1 0 0 0 0 70 0.7ns* 5 -10b 1 0 0 0 0 0 0 0 80 0.8ns* 5 11 dimm configuration type 0 0 0 0 0 0 0 0 00 non-parity 12 refresh rate/type 1 0 0 0 0 0 1 0 82 7.8 s self refresh 13 primary sdram width 0 0 0 1 0 0 0 0 10 16 14 error checking sdram width 0 0 0 0 0 0 0 0 00 not used 15 sdram device attributes: minimum clock delay back-to-back column access 0 0 0 0 0 0 0 1 01 1 clk 16 sdram device attributes: burst length supported 0 0 0 0 1 1 1 0 0e 2, 4, 8 17 sdram device attributes: number of banks on sdram device 0 0 0 0 0 1 0 0 04 4 18 sdram device attributes: /cas latency 0 0 0 0 1 1 0 0 0c 2, 2.5 19 sdram device attributes: /cs latency 0 0 0 0 0 0 0 1 01 0 20 sdram device attributes: /we latency 0 0 0 0 0 0 1 0 02 1 21 sdram module attributes 0 0 1 0 0 0 0 0 20 unbuffered 22 sdram device attributes: general 1 0 0 0 0 0 0 0 80 0.2v 23 minimum clock cycle time at clx - 0.5 -a75b 0 1 1 1 0 1 0 1 75 cl = 2* 5 -b75b/10b 1 0 1 0 0 0 0 0 a0 24 maximum data access time (tac) from clock at clx - 0.5 -a75b/b75b 0 1 1 1 0 0 0 0 70 0.7ns* 5 -10b 1 0 0 0 0 0 0 0 80 0.8ns* 5 25 minimum clock cycle time at clx - 1 0 0 0 0 0 0 0 0 00 26 maximum data access time (tac) from clock at clx - 1 0 0 0 0 0 0 0 0 00 27 minimum row precharge time (trp) 0 1 0 1 0 0 0 0 50 20ns
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 28 minimum row active to row active delay (trrd) 0 0 1 1 1 1 0 0 3c 15ns 29 minimum /ras to /cas delay (trcd) 0 1 0 1 0 0 0 0 50 20ns 30 minimum active to precharge time (tras) -a75b/b75b 0 0 1 0 1 1 0 1 2d 45ns -10b 0 0 1 1 0 0 1 0 32 50ns 31 module bank density 0 0 1 0 0 0 0 0 20 1 bank/ 2 bank 128 mb 32 address and command setup time before clock (tis) -a75b/b75b 1 0 1 1 0 0 0 0 b0 1.1ns* 5 -10b 1 1 0 0 0 0 0 0 c0 1.2ns* 5 33 address and command hold time after clock (tih) -a75b/b75b 1 0 1 1 0 0 0 0 b0 1.1ns* 5 -10b 1 1 0 0 0 0 0 0 c0 1.2ns* 5 34 data input setup time before clock (tds) -a75b/b75b 0 1 0 1 0 0 0 0 50 0.5ns* 5 -10b 0 1 1 0 0 0 0 0 60 0.6ns* 5 35 data input hold time after clock (tdh) -a75b/b75b 0 1 0 1 0 0 0 0 50 0.5ns* 5 -10b 0 1 1 0 0 0 0 0 60 0.6ns* 5 36 to 40 superset information 0 0 0 0 0 0 0 0 00 future use 41 active command period (trc) -a75b/b75b 0 1 0 0 0 0 0 1 41 65ns* 5 -10b 0 1 0 0 0 1 1 0 46 70ns* 5 42 auto refresh to active/ auto refresh command cycle (trfc) -a75b/b75b 0 1 0 0 1 0 1 1 4b 75ns* 5 -10b 0 1 0 1 0 0 0 0 50 80ns* 5 43 sdram tck cycle max. (tck max.) 0 0 1 1 1 1 0 0 3c 15ns* 5 44 dout to dqs skew -a75b/b75b 0 0 1 1 0 0 1 0 32 500ps* 5 -10b 0 0 1 1 1 1 0 0 3c 600ps* 5 45 data hold skew (tqhs) -a75b/b75b 0 1 1 1 0 1 0 1 75 750ps* 5 -10b 1 0 1 0 0 0 0 0 a0 1000ps* 5 46 to 61 superset information 0 0 0 0 0 0 0 0 00 future use 62 spd revision 0 0 0 0 0 0 0 0 00 initial
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 7 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 63 checksum for bytes 0 to 62 -a75b 1 0 0 1 1 1 0 0 9c 156 -b75b 1 1 0 0 1 1 0 0 cc 204 -10b 0 1 1 1 1 0 1 1 7b 123 64 manufacturer?s jedec id code 0 0 0 0 0 1 1 1 07 hitachi 65 to 71 manufacturer?s jedec id code 0 0 0 0 0 0 0 0 00 72 manufacturing location * 2 (ascii-8bit code) 73 module part number 0 1 0 0 1 0 0 0 48 h 74 module part number 0 1 0 0 0 0 1 0 42 b 75 module part number 0 0 1 1 0 1 0 1 35 5 76 module part number 0 0 1 1 0 1 0 0 34 4 77 module part number 0 1 0 0 0 0 0 1 41 a 78 module part number 0 0 1 1 0 0 1 0 32 2 79 module part number 0 0 1 1 0 1 0 1 35 5 80 module part number 0 0 1 1 0 1 1 0 36 6 81 module part number 0 0 1 1 1 0 0 0 38 8 82 module part number 0 1 0 0 1 0 1 1 4b k 83 module part number 0 1 0 0 1 1 1 0 4e n 84 module part number 0 0 1 0 1 1 0 1 2d ? 85 module part number -a75b 0 1 0 0 0 0 0 1 41 a -b75b 0 1 0 0 0 0 1 0 42 b -10b 0 0 1 1 0 0 0 1 31 1 86 module part number -a75b/b75b 0 0 1 1 0 1 1 1 37 7 -10b 0 0 1 1 0 0 0 0 30 0 87 module part number -a75b/b75b 0 0 1 1 0 1 0 1 35 5 -10b 0 1 0 0 0 0 1 0 42 b 88 module part number -a75b/b75b 0 1 0 0 0 0 1 0 42 b -10b 0 0 1 0 0 0 0 0 20 (space) 89 to 90 module part number 0 0 1 0 0 0 0 0 20 (space) 91 revision code 0 0 1 1 0 0 0 0 30 initial 92 revision code 0 0 1 0 0 0 0 0 20 (space) 93 manufacturing date year code (bcd) 94 manufacturing date week code (bcd) 95 to 98 module serial number * 3 99 to 127 m anufacturer specific data * 4
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 8 notes: 1. all serial pd data are not protected. 0: serial data, ?driven low?, 1: serial data, ?driven high? these spd are based on jedec committee ballot jc-42.5-99-129. 2. byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows ?j? on ascii code.) 3. bytes 95 through 98 are assembly serial number. 4. all bits of 99 through 127 are not defined (?1? or ?0?). 5. these specifications are defined based on component specification, not module.
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 9 block diagram dm0 sdrams (d0 to d7) sdrams (d0 to d7) ba0 to ba1 sdrams (d0 to d7) cke0 sdrams (d0 to d3) cke1 sdrams (d4 to d7) vccspd spd vref sdrams (d0 to d7) vcc sdrams (d0 to d7), and vss vccid vcc vccq open sdrams (d0 to d7), spd serial pd sda a0 a1 a2 wp scl sa0 sa1 sa2 u0 sda scl notes : 1. dq wiring may differ from that described in this drawing; however dq/dm/dqs relationships are maintained as shown. vccid strap connections: (for memory device vcc, vccq) strap out (open): vcc = vccq strap in (closed): vcc vccq 2. the sda pull-up registor is reguired due to the open-drain/open-collector output. 3. the scl pull-up registor is recommended, because of the normal scl lime inactive "high" state. dqs0 dq0 to dq7 8 d0 /ras /cas /we a0 to an sdrams (d0 to d7) sdrams (d0 to d7) 4 loads ck0 /ck0 4 loads ck1 /ck1 10 pf ck2 /ck2 /s0 /s1 /s d2 /s ldqs ldm i/o0 to i/o7 * d0 to d7 : 256m bits ddr sdram u0 : 2k bits eeprom rs : 22 ? r s r s r s dm1 dqs1 dq8 to dq15 8 udqs udm i/o8 to i/o15 r s r s r s dm4 dqs4 dq32 to dq39 8 r s r s r s dm5 dqs5 dq40 to dq47 8 r s r s r s ldqs ldm i/o0 to i/o7 udqs udm i/o8 to i/o15 dm2 dqs2 dq16 to dq23 8 d1 /s d3 /s ldqs ldm i/o0 to i/o7 r s r s r s dm3 dqs3 dq24 to dq31 8 udqs udm i/o8 to i/o15 d4 /s ldqs ldm i/o0 to i/o7 udqs udm i/o8 to i/o15 d5 /s ldqs ldm i/o0 to i/o7 udqs udm i/o8 to i/o15 r s r s r s dm6 dqs6 dq48 to dq55 8 r s r s r s dm7 dqs7 dq56 to dq63 8 r s r s r s ldqs ldm i/o0 to i/o7 udqs udm i/o8 to i/o15 d6 /s ldqs ldm i/o0 to i/o7 udqs udm i/o8 to i/o15 d7 /s ldqs ldm i/o0 to i/o7 udqs udm i/o8 to i/o15
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 10 logical clock net structure dram1 4dram loads 120 ? dimm connector dram2 dram3 dram4
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 11 pin functions (1) ck (clk), /ck (/clk) (input pin): the ck and the /ck are the master clock inputs. all inputs except dms, dqss and dqs are referred to the cross point of the ck rising edge and the vref level. when a read operation, dqss and dqs are referred to the cross point of the ck and the /ck. when a write operation, dms and dqs are referred to the cross point of the dqs and the vref level. dqss for write operation are referred to the cross point of the ck and the /ck. /s (/cs) (input pin): when /s is low, commands and data can be input. when /s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins): these pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. see "command operation". a0 to a12 (input pins): row address (ax0 to ax12) is determined by the a0 to the a12 level at the cross point of the ck rising edge and the vref level in a bank active command cycle. column address (ay0 to ay8) is loaded via the a0 to the a8 at the cross point of the ck rising edge and the vref level in a read or a write command cycle. this column address becomes the starting address of a burst operation. a10 (ap) (input pin): a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1, ba0 is precharged. if a10 = high when read or write command, auto-precharge function is enabled. while a10 = low, auto-precharge function is disabled. ba0, ba1 (input pin): ba0/ba1 are bank select signals. the memory array is divided into bank 0, bank 1, bank 2 and bank 3. if ba1 = low and ba0 = low, bank 0 is selected. if ba1 = high and ba0 = low, bank 1 is selected. if ba1 = low and ba0 = high, bank 2 is selected. if ba1 = high and ba0 = high, bank 3 is selected. cke (input pin): cke controls power down and self-refresh. the power down and the self-refresh commands are entered when the cke is driven low and exited when it resumes to high. the cke level must be kept for 1 ck cycle (= lckepw) at least, that is, if cke changes at the cross point of the ck rising edge and the vref level with proper setup time tis, at the next ck rising edge cke level must be kept with proper hold time tih. pin functions (2) dq (input and output pins): data are input to and output from these pins. dqs (input and output pin): dqs provide the read data strobes (as output) and the write data strobes (as input). dm (input pins): dm is the reference signal of the data input mask function. dms are sampled at the cross point of dqs and vref vcc and vccq (power supply pins): 2.5v is applied. (vcc is for the internal circuit and vccq is for the output buffer.) vccspd (power supply pin): 2.5v is applied (for serial eeprom). vss (power supply pin): ground is connected. detailed operation part, ac characteristics and timing waveforms refer to the hm5425161b/hm5425801b/hm5425401b series datasheet (e0086h).
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 12 electrical specifications absolute maximum ratings parameter symbol value unit note voltage on any pin relative to vss vt ?1.0 to +4.6 v 1 supply voltage relative to vss vcc, vccq ?1.0 to +4.6 v 1 short circuit output current iout 50 ma power dissipation pt 8 w operating temperature topr 0 to +65 c storage temperature tstg ?50 to +100 c notes: 1. respect to vss. dc operating conditions (ta = 0 to +65c) parameter symbol min. typ max. unit notes supply voltage vcc, vccq 2.3 2.5 2.7 v 1, 2 vss 0 0 0 v input reference voltage vref 1.15 1.25 1.35 v 1 termination voltage vtt vref ? 0.04 vref vref + 0.04 v 1 dc input high voltage vih vref + 0.18 ? vccq + 0.3 v 1, 3 dc input low voltage vil ?0.3 ? vref ? 0.18 v 1, 4 dc input signal voltage vin (dc) ?0.3 ? vccq + 0.3 v 5 dc differential input voltage vswing (dc) 0.36 ? vccq + 0.6 v 6 notes: 1. all parameters are referred to vss, when measured. 2. vccq must be lower than or equal to vcc. 3. vih is allowed to exceed vcc up to 4.6v for the period shorter than or equal to 5ns. 4. vil is allowed to outreach below vss down to ?1.0v for the period shorter than or equal to 5ns. 5. vin (dc) specifies the allowable dc execution of each differential input. 6. vswing (dc) specifies the input differential voltage required for switching.
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 13 dc characteristics 1 (ta = 0 to 65c, vcc, vccq = 2.5v 0.2v, vss = 0v) parameter symbol grade max. unit test condition notes operating current (actv-pre) icc0 -a75b -b75b -10b 600 560 480 ma cke vih, trc = min. 1, 2, 5 operating current (actv-read-pre) icc1 -a75b -b75b -10b 820 760 680 ma cke vih, bl = 2, cl = 2.5, trc = min. 1, 2, 5 idle power down standby current icc2p -a75b -b75b -10b 144 120 96 ma cke vil 4 idle standby current icc2n -a75b -b75b -10b 320 280 240 ma cke vih, /cs vih 4 active power down standby current icc3p -a75b -b75b -10b 200 160 120 ma cke vil 3 active standby current icc3n -a75b -b75b -10b 400 360 320 ma cke vih, /cs vih tras = max. 3 operating current (burst read operation) icc4r -a75b -b75b -10b 1220 1160 1100 ma cke vih, bl = 2, cl = 2.5 1, 2, 5, 6 operating current (burst write operation) icc4w -a75b -b75b -10b 1160 1100 1040 ma cke vih, bl = 2, cl = 2.5 1, 2, 5, 6 auto refresh current icc5 -a75b -b75b -10b 1020 980 880 ma trfc = min., input vil or vih self refresh current icc6 24 ma input vcc ? 0.2v input 0.2v. notes. 1. these icc data are measured under condition that dq pins are not connected. 2. one bank operation. 3. one bank active. 4. all banks idle. 5. command/address transition once per one cycle. 6. data/data mask transition twice per one cycle. 7. the icc data on this table are measured with regard to tck = min. in general. dc characteristics 2 (ta = 0 to 65c, vcc, vccq = 2.5v 0.2v, vss = 0v) parameter symbol min. max. unit test condition notes input leakage current ili ?10 10 a vcc vin vss output leakage current ilo ?10 10 a vcc vout vss output high voltage voh vtt + 0.76 ? v ioh (max.) = ?15.2ma output low voltage vol ? vtt ? 0.76 v iol (min.) = 15.2ma
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 14 pin capacitance (ta = 25c, vcc, vccq = 2.5v 0.2v) [parameter symbol pins min. max. unit notes input capacitance ci1 address, /ras, /cas, /we ? 60 pf 1 input capacitance ci2 cke, /s ck, /ck ? 40 pf 1 data and dqs input/output capacitance co dq, dqs, dm ? 27 pf 1, 2 notes: 1. these parameters are measured on conditions: f = 100mhz, vout = vccq/2, ? vout = 0.2v. 2. dout circuits are disabled. timing parameter measured in clock cycle for unbuffered dimm number of clock cycle parameter symbol min. max. write to pre-charge command delay (same bank) twpd 3 + bl/2 read to pre-charge command delay (same bank) trpd bl/2 write to read command delay (to input all data) twrd 2 + bl/2 burst stop command to write command delay (cl = 2) tbstw 2 (cl = 2.5) tbstw 3 burst stop command to dq high-z (cl = 2) tbstz 2 (cl = 2.5) tbstz 2.5 read command to write command delay (to output all data) (cl = 2) trwd 2 + bl/2 (cl = 2.5) trwd 3 + bl/2 pre-charge command to high-z (cl = 2) thzp 2 (cl = 2.5) thzp 2.5 write command to data in latency twcd 1 write recovery twr 2 dm to data in latency tdmd 0 register set command to active or register set command tmrd 2 self refresh exit to non-read command tsnr 10 self refresh exit to read command tsrd 200 power down entry tpden 1 power down exit to command input tpdex 1 cke minimum pulse width tckepw 1
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 15 physical outline r0.50 0.20 r0.50 0.20 2x 1.80 63.60 67.60 18.45 11.55 2.15 4.20 4.20 47.40 47.40 2.45 2.15 2.45 11.40 11.40 31.75 20.0 6.00 1 2 unit: mm 1.00 0.10 4.00 4.00 0.10 3.80 (datum -a-) ab 4x full r 2.00 min. 199 1.50 200 component area (front) component area (back) detail b 0.25 max 2.55 0.45 0.03 0.60 1.80 1.00 0.10 4.00 0.10 (datum -a-) detail a full r (datum -a-) eca-ts2-0019-01
hb54a2568kn-a75b/b75b/10b preliminary data sheet e0148h20 (ver. 2.0) 16 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. in particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0202 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107

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